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CY7C277
32K x 8 Reprogrammable Registered PROM
Features
* Windowed for reprogrammability * CMOS for optimum speed/power * High speed -- 30-ns address set-up -- 15-ns clock to output * Low power -- 60 mW (commercial) -- 715 mW (military) * Programmable address latch enable input * Programmable synchronous or asynchronous output enable * On-chip edge-triggered output registers * EPROM technology, 100% programmable * Slim 300-mil, 28-pin plastic or hermetic DIP * 5V 10% VCC, commercial and military * TTL-compatible I/O * Direct replacement for bipolar PROMs * Capable of withstanding greater than 2001V static discharge
Logic Block Diagram
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
X ADDRESS ROW DECODER 1 OF 256 256 x 1024 PROGRAMMABLE ARRAY 8-BIT 1 OF 128 MUX
Pin Configurations
O7 O6 O5
8-BIT EDGETRIGGERED REGISTER
DIP/Flatpack Top View
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A10 A11 A12 A13 A14 ALE CP E/ES O7 O6 O5 O4 O3
15-BIT ADDRESS TRANSPARENT/ LATCH
O4 O3 O2 O1
Y ADDRESS COLUMN DECODER 1 OF 32
ALE PROGRAMMABLE CP/ALE OPTIONS
O0
CP
ALE
LCC/PLCC (Opaque Only) Top View
E/E S CP
D C Q PROGRAMMABLE MULTIPLEXER
A6 A5 A4 A3 A2 A1 A0 NC O0
4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 O1 O2 GND NC O3 O4 O5
A7 A8 A9 NC V CC A10 A11 A12 A13 A14 NC ALE CP E/ES O7 O6
Selection Guide
7C277-30 Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Current (mA) Com'l Mil 30 15 120 7C277-40 40 20 120 130 7C277-50 50 25 120 130
Cypress Semiconductor Corporation Document #: 38-04006 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 4, 2002
CY7C277
Functional Description
The CY7C277 is a high-performance 32K word by 8-bit CMOS PROMs. It is packaged in the slim 28-pin 300-mil package. The ceramic package may be equipped with an erasure window; when exposed to UV light, the PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide algorithms. The CY7C277 offers the advantages of low power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be 100% tested, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming. On the 7C277, the outputs are pipelined through a master-slave register. On the rising edge of CP, data is loaded into the 8-bit edge triggered output register. The E/ES input provides a programmable bit to select between asynchronous and synchronous operation. The default condition is asynchronous. When the asynchronous mode is selected, the E/ES pin operates as an asynchronous output enable. If the synchronous mode is selected, the E/ES pin is sampled on the rising edge of CP to enable and disable the outputs. The 7C277 also provides a programmable bit to enable the Address Latch input. If this bit is not programmed, the device will ignore the ALE pin and the address will enter the device asynchronously. If the ALE function is selected, the address enters the PROM while the ALE pin is active, and is captured when ALE is deasserted. The user may define the polarity of the ALE signal, with the default being active HIGH.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................-65C to +150C Ambient Temperature with Power Applied.................................................-55C to +125C Supply Voltage to Ground Potential .................-0.5V to +7.0V (Pin 24 to Pin 12) DC Voltage Applied to Outputs in High Z State.....................................................-0.5V to +7.0V DC Input Voltage ................................................. -3.0V to +7.0V DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V UV Erasure................................................... 7258 Wsec/cm2 Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Military
[2]
Ambient Temperature 0C to +70C -40C to +85C -55C to +125C
VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3, 4]
7C277-30 Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC VPP IPP VIHP VILP Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current Power Supply Current Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 3.0 0.4 0 < VOUT < VCC, Output Disabled[5] VCC = Max., VOUT = 0.0V
[6]
7C277-40, 50 Min. 2.4 Max. 0.4 2.0 VCC 0.8 -10 -40 -20 +10 +40 -90 120 130 12 3.0 0.4 13 50 Unit V V V V A A mA mA V mA V V
Test Conditions VCC = Min., IOH = - 2.0 mA VCC = Min., IOL = 8.0 mA Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs GND < VIN < VCC
Min. 2.4
Max. 0.4
2.0
VCC 0.8
-10 -40 -20
+10 +40 -90 120
Note 4
VCC = Max., CS > VIH Commercial IOUT = 0 mA Military 12
13 50
Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See "Introduction to CMOS PROMs" in this Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04006 Rev. **
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CY7C277
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms[4]
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 500 (658 MIL) 5V OUTPUT R2 5 pF 333 (403 MIL) INCLUDING JIG AND SCOPE R2 333 (403 MIL) R1 500 (658 MIL) ALL INPUT PULSES 3.0V GND < 5 ns 90% 10% 90% 10% < 5 ns
(a) NormalLoad
Equivalent to: THEVENIN EQUIVALENT OUTPUT 200
(b) High Z Load
2.0V
OUTPUT
250
1.9V
Commercial
Military
CY7C277 Switching Characteristics Over the Operating Range[3, 4]
7C277-30 Parameter tAL tLA tLL tSA tHA tSES tHES tCO tPWC tLZC[7] tHZC tLZE[8] tHZE[8] Description Address Set-Up to ALE Inactive Address Hold from ALE Inactive ALE Pulse Width Address Set-Up to Clock HIGH Address Hold from Clock HIGH ES Set-Up to Clock HIGH ES Hold from Clock HIGH Clock HIGH to Output Valid Clock Pulse Width Output Valid from Clock HIGH Output High Z from Clock HIGH Output Valid from E LOW Output High Z from E HIGH 15 15 15 15 15 Min. 5 10 10 30 0 12 5 15 20 20 20 20 20 Max. 7C277-40 Min. 10 10 10 40 0 15 10 20 20 30 30 30 30 Max. 7C277-50 Min. 10 15 15 50 0 15 10 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 7. Applies only when the synchronous (ES) function is used. 8. Applies only when the asynchronous (E) function is used.
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CY7C277
Architecture Configuration Bits
Architecture Bit ALE ALEP E/ES Architecture Verify D7 - D0 D1 D2 D0 0 = DEFAULT 1 = PGMED 0 = DEFAULT 1 = PGMED 0 = DEFAULT 1 = PGMED Input Transparent Input Latched ALE = Active HIGH ALE = Active LOW Asynchronous Output Enable (E) Synchronous Output Enable (ES) Architecture Byte (8000) RAM Data Data . . . Data Control Byte
D7 D0 C7 C6 C5 C4 C3 C2 C1 C0
Function
Bit Map
Programmer Address (Hex.) 0000 . . . 7FFF 8000
Timing Diagram (Input Latched)[9]
A0 - A14 tAL ALE tLL tLA tSA tHA
ES (SYNCH) CP
tHES tCO
tSES tHZC
tPWC
tHES
tSES
tPWC HIGH Z
tLZC HIGHZ
O0 - O7 tHZE ES (ASYNCH) tLZE
Timing Diagram (Input Transparent)
A0 - A14 tSA ES (SYNCH) CP tHA
tHES tCO
tSES tHZC
tPWC
tHES
tSES
tPWC HIGH Z
tLZC HIGHZ tHZE tLZE
O0 - O7
ES (ASYNCH)
Note: 9. ALE is shown with positive polarity.
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CY7C277
Programming Information
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed Table 1. Mode Selection Pin Function[10] Read or Output Disable Mode Read Output Disable Program Program Verify Program Inhibit Blank Check
Note: 10. X = "don't care" but not to exceed VCC 5%.
programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
A14-A0 A14-A0 A14-A0 A14-A0 A14-A0 A14-A0 A14-A0 A14-A0
E, ES VFY VIL VIH VIHP VILP VIHP VILP
CP PGM VIH X VILP VIHP/VILP VIHP VIHP/VILP
ALE VPP VIL X VPP VPP VPP VPP
O7-O0 D7-D0 O7-O0 High Z D7-D0 O7-O0 High Z O7-O0
Other
DIP Top View
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A10 A11 A12 A13 A14 VPP PGM VFY D7 D6 D5 D4 D3
LCC/PLCC (Opaque Only) Top View
A7 A8 A9 NC VCC A10 A11 A6 A5 A4 A3 A2 A1 A0 NC D0 4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 D1 D2 GND NC D3 D4 D5 A12 A13 A14 NC VPP PGM VFY D7 D6
Figure 1. Programming Pinouts
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CY7C277
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 NORMALIZED I CC 1.4 1.2 1.0 0.8 0.6 4.0 TA =25C f = fMAX 4.5 5.0 5.5 6.0 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME 1.2 1.0 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE
NORMALIZED ICC
1.1
1.0
0.8
0.9
0.6 TA =25C 0.4 4.0 4.5 5.0 5.5 6.0
0.8 -55
25
125
SUPPLYVOLTAGE (V)
AMBIENTTEMPERATURE (C)
SUPPLYVOLTAGE (V)
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SET-UP TIME vs. TEMPERATURE NORMALIZED SET -UP TIME 1.6 1.4 1.2 1.0 0.8 0.6 -55
OUTPUT SOURCE CURRENT vs. VOLTAGE 60 50 (ns) 40 30 20 10 0 0 1.0 2.0 3.0 4.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
DELTA AA t
TA =25C VCC =4.5V 0 200 400 600 800 1000
25
125
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
OUTPUT SINK CURRENT (mA)
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 175 150 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
OUTPUT VOLTAGE (V)
C277-12
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CY7C277
Ordering Information[11]
Speed (ns) 30 Ordering Code CY7C277-30JC CY7C277-30PC CY7C277-30WC 40 CY7C277-40JC CY7C277-40PC CY7C277-40WC CY7C277-40DMB CY7C277-40KMB CY7C277-40LMB CY7C277-40QMB CY7C277-40TMB CY7C277-40WMB 50 CY7C277-50JC CY7C277-50PC CY7C277-50WC CY7C277-50DMB CY7C277-50KMB CY7C277-50LMB CY7C277-50QMB CY7C277-50TMB CY7C277-50WMB Package Name J65 P21 W22 J65 P21 W22 D22 K74 L55 Q55 T74 W22 J65 P21 W22 D22 K74 L55 Q55 T74 W22 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Lead Rectangular Cerpack 32-Pin Rectangular Leadless Chip Carrier 32-Pin Windowed Rectangular Leadless Chip Carrier 28-Lead Windowed Cerpack 28-Lead (300-Mil) Windowed CerDIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Lead Rectangular Cerpack 32-Pin Rectangular Leadless Chip Carrier 32-Pin Windowed Rectangular Leadless Chip Carrier 28-Lead Windowed Cerpack 28-Lead (300-Mil) Windowed CerDIP Military Commercial Military Commercial Operating Range Commercial
Note: 11. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tSA tHA tCO Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
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CY7C277
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
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CY7C277
Package Diagrams (continued)
28-Lead Rectangular Cerpack K74
MIL-STD-1835 F-11 Config. A
51-80061
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CY7C277
Package Diagrams (continued)
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068
28-Lead (300-Mil) Molded DIP P21
51-85014-B
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CY7C277
Package Diagrams (continued)
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
51-80103-*A
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CY7C277
Package Diagrams (continued)
28-Lead Windowed Cerpack T74
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C277
Document Title: CY7C277 32K x 8 Programmable Registered PROM Document Number: 38-04006 REV. ** ECN NO. 113862 Issue Date 3/8/02 Orig. of Change DSG Description of Change Change from Spec number: 38-00085 to 38-04006
Document #: 38-04006 Rev. **
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